Designers and semiconductor device manufacturers constantly strive to develop smaller devices from wafers, recognizing that circuits with smaller features generally produce greater speeds and increased yield (numbers of usable chips produced from a standard semiconductor wafer). It is desirable to produce wafers with consistent dimensions, particularly as to the line widths printed on the devices. However, with smaller devices (where the critical dimension of the printed features are smaller than the exposure wavelength) the difficulty in meeting critical dimension tolerances increases. Certain wave front engineering techniques such as optical proximity correction (OPC) and phase shift mask (PSM) techniques are often applied to reticles to improve lithographic performance and extend the useful lifetime of optical exposure tools. The changes produced by these techniques are referred to as wavefront engineering features. Phase shift mask (PSM) techniques (strong-alternating, weak-embedded, and attenuating) are used mainly to improve lithographic resolution, improve depth of focus, and monitor the lithographic stepper or scanner performance using focus monitors. Optical proximity correction is a wavefront engineering technique wherein a modification of the photomask pattern (binary changes, i.e., adding or subtracting chrome on the mask) is made to compensate for changes in feature shape and size that occur during pattern transfer from the mask to the wafer. These feature changes may be caused by extra exposure due to the presence of adjacent lithographic features, a limitation in the wafer stepper/scanner, or a variation in the activity of a given wafer process step. OPC is also used on phase shifted masks to maximize the benefit gained from PSM technology. While OPC techniques are often used to correct for pattern fidelity error (a reduction in the quality of the aerial image) and improve process latitudes, OPC does little for improving resolution. In addition to OPC and PSM technologies, a variety of other wavefront engineering techniques are currently in use. For example, sub-resolution features called “scatter bars” (binary mask additions or sub-resolution mask patterns which do not print) improve lithographic behavior of small isolated and quasi-dense features by adjusting the shape of the aerial image—simply an extension of OPC technology.
Minor variations in process parameters, such as changes in focus and exposure dose on photolithographic exposure equipment (scanners/steppers), may cause the critical dimensions (CD) on the wafers to fall outside acceptable semiconductor manufacturing tolerances (typical CD specifications are +/−8%). A large number of process parameters may affect the dimensions of a resist pattern on a silicon wafer. Some of the most significant parameters include: resist thickness, focus position, exposure dose, resist pre and post bake temperatures and development temperature and time. While photolithographic exposure tools and photolithographic resist tracks continuously monitor and adjust for small fluctuating changes in the process conditions (bake times, exposure dose, focus, etc.,) the resulting resist feature size or critical dimension is a complex result of all process variables. Typically, semiconductor manufacturing facilities correct for process variation (drifting CD's) by adjusting only the exposure dose (e.g. hourly changes). This tends to provide the most economically viable solution.
Photolithography is one of the most important steps of the semiconductor manufacturing process. Most integrated circuits are made using a photolithographic processes, which process uses photolithographic masks and an associated light or radiation source to project a circuit image onto a wafer. Referring to FIG. 1, for example, a simplified diagram of a lithography system 2 is shown. By way of example, the lithography system may correspond to a stepper or scanning system. The lithography system I typically includes a light or radiation source 3 and a first set of optics 4 that illuminate a mask 5 having a circuit pattern 6 disposed thereon. In order to form the circuit pattern, the mask 6 may include opaque portions and/or transmissive portions. As is generally well known, the opaque portions block the light from passing through the mask 6 while the transmissive portions allow the light to pass therethrough. In some cases, the transmissive portions may constitute phase shifted areas. Phase shifted areas tend to alter the phase of the light or radiation passing through the mask. The lithography system 2 also includes a second set of optics 7 that pick up the transmitted light or radiation and focuses (or images) it onto a surface 9 of a semiconductor wafer 8 thus writing the pattern of the mask 6 onto the surface 9 of the semiconductor wafer 8. In most cases, the semiconductor wafer 8 includes a layer of photoresist that when exposed to the patterned light or radiation forms the pattern of the mask onto the wafer.
During most photolithographic processes, such as the one depicted in FIG. 1, a semiconductor wafer is coated with a light sensitive material called a photoresist or resist (example; chemically amplified resist (CAR)) and is exposed with an actinic light source (excimer laser, mercury lamp, etc.,). The exposure light passes through a photomask and is imaged via projection optics onto the resist coated wafer forming a reduced image (typically 4× or 5×) of the photomask in the photoresist. For positive chemically amplified resists (CARs), the actinic light source typically causes the production of photoacids that diffuse during post exposure bake and allow the resist to be rinsed away by an aqueous developer only in those regions receiving most of the exposure dose.
A final step in the photolithographic process may involve etching the resist-coated wafers using complex plasma chemistry to attack the semiconductor material not covered with photoresist, and following etch, the resist coated wafers are cleaned and sent to a scanning electron microscope or other metrology for final lithographic inspection. Since prior to etching, it is possible to repeat the lithographic processing if a problem is detected in time, and after the photoresist wafers are physically etched it is too late to correct a problem with the photolithographic imaging process, precise control of the printing process is desired to ensure that the device line widths forming the pattern on the wafer fall within tolerance. Thus, following the develop process the resist patterned wafers may be sent to a metrology station to measure the critical dimensions or shape of the patterned resist features. Typical metrology tools include scatterometers, scanning electron microscopes and atomic force microscopes.
One problem that has been encountered during lithographic processes, and which needs monitoring, is the misfocus found between the actual focus plane of the optical system used for the process and the ideal focus plane, where the best or “ideal” focus position for target printing is usually within the resist layer. For example, referring back to FIG. 1, the light or radiation follows an optical path that corresponds to the Z axis. The first and second set of optics as well as the mask and the wafer are thus positioned orthogonal to the optical path in different X&Y planes. With this in mind, the second set of optics generally focuses the light on a specific X&Y plane (not shown) positioned along the Z axis. This plane is generally referred to as the ideal focus plane. When the system is out of focus, the stepper focus plane may be offset relative to the ideal focus position. As should be appreciated, misfocus generally has a sign and magnitude corresponding to the Z axis displacement. The sign corresponds to the direction of the displacement (e.g., positive or negative), and the magnitude corresponds to the amount of displacement (e.g., the actual distance between planes). The displacement may be caused by many factors. For example, the second set of optics and/or the wafer may be mis-aligned (e.g., tilted) or they may be positioned in the wrong plane along the Z axis. Deviations on the surface of the wafer itself may contribute to misfocus.
As mentioned above, misfocus may adversely affect the printed pattern on the wafer. For example, misfocus may cause increases or decreases in the width of the lines printed on the wafer, (i.e., linewidth is a function of focus). The linewidth generally determines the speed and the timing across the circuit and thus misfocus may cause one portion of the chip to run faster or slower than another portion of the chip. In most cases, the chip is clocked to the slowest portion thereby reducing chip performance and most often the selling price of the chip. In addition, misfocus may cause open or shorted circuits such that the chip must be discarded or reworked.
Under certain circumstances, when the magnitude of the misfocus is sufficiently great, the intensity of exposure (Iexposure) experienced by some or all of the photo resist, which is meant to be exposed, may not exceed an intensity threshold value (Ithreshold), which intensity threshold value (Ithreshold) may be required to make the photo resist soluble. For example, if the misfocus results in the focal plain of the projected pattern being considerably above the actual surface of the photo resist layer, the surface of the photo resist may experience exposure with an intensity level above the threshold intensity, but due to optical divergence of the beam, portions of the photo resist below the surface may not experience sufficient exposure intensity and may not dissolve. If the misfocus results in the focal plain being considerably below the photo resist layer, the intensity of the beam at the surface of the photo resist may not be sufficiently converged, focused or dense to have an intensity which exceeds the require threshold value, and the surface of the photo resist may not experience sufficient exposure to make it soluble using an subsequent aqueous developer.
Presently, focus is determined by exposing a pattern through a range of focus settings, and then inspecting the resultant patterns for the best looking images or by using an aerial image monitor to determine the spatial location of the best focus.
Presently, one monitoring technique used is a lot sampling of the resist imaged wafers to determine if the line widths (critical dimensions) have fallen outside an acceptable range prior to etch. However, given the extremely small sizes of the devices, for example device sizes of 0.15 micron or smaller, expensive and slow metrology techniques are necessary. With these dimensions, one of the few effective tools currently in use to measure line widths is a scanning electron microscope (SEM). The wafers must be removed from their processing location and transported to the SEM. Moreover, the time required for SEM inspections is so extensive that a typical sampling rate may not detect a process drift until after a large number of wafers have been etched.
Other monitoring metrologies include; scatterometry techniques (ellipsometry, variable angle, reflection) using complex and expensive look-up libraries, and optical CD techniques utilizing an inexpensive optical metrology tool and dual toned line shortening (“schnitzl”) arrays to indirectly measure the critical dimensions of photoresist patterned wafers using line-end shortening techniques. While the OCD technique is fast and inexpensive, the technique may or may not have the optimum process sensitivity that is required for day to day production monitoring routines. In practice, the OCD technique can be used to determine both focus and exposure drifts by building a second order polynominal description of the complex CD drift with changes in focus and exposure. However, the ability to determine absolute direction of focus drifts requires the additional printing of test fields out of focus—which takes valuable exposure time and space on a semiconductor wafer.